IBM breakthrough improves carbon nanotube scaling below 10nm

Over the past few years, IBM has poured a great deal of time and effort into researching carbon nanotubes (CNTs). The existence of single-walled carbon nanotubes and their marvelous semiconductor properties occurred independently at both NEC and IBM, and Big Blue has been interested in capitalizing on that discovery for well over a decade. IBM researchers have now published a paper in which they claim to have demonstrated highly beneficial scaling capabilities in carbon nanotubes.
We’ve discussed the difficulties of scaling semiconductors as the distance between features shrinks with every passing generation, but the specific breakthrough IBM is claiming is in an area of chip design we haven’t discussed much. In conventional silicon (or conventional carbon nanotubes, for that matter), there’s been a known problem — as semiconductors continue to shrink, the contact area between the metal and semiconductor hasn’t been scaling. Generally speaking, smaller contact areas lead to increased resistance, and increased resistance means higher heat. Manufacturers have fought back against these trends with a variety of methods, but the lack of contact scaling is one of the fundamental barriers to pushing silicon to ever-smaller sizes.

Image by IBM Research

IBM thinks its carbon nanotube technology could solve that problem. EETimes has an excellent write-up of the technology, though it hilariously refers to EUV lithography as “already in place,” — a declaration that I’m certain would surprise both Intel and TSMC. With our recent breakthrough, “Shu-Jen Han, IBM manager of nanoscale science and technology at its T.J. Watson Research Center (Yorktown, Heights) told EE Times, “we now know how to scale [the contact] so it is no longer the limiting factor for carbon nanotube transistors. Our new contacts are measured in angstroms and have just 36 k-ohms of resistance, including both ends.”
The new approach involves welding — nanowelding — a nanotube with molybdenum before they are self-aligned as transistor channels. The final step is to heat the assembly to 850C, melting the molybdenum off and creating carbide. According to Richard Doherty, of Envision Engineering, this solution gives IBM a unique advantage in scaling all the way down to 1.8nm. According to EETimes, IBM may be prepping this technology to be ready at the 5nm node, for introduction at 3nm and below. With the method already proven in theory at 9nm, there seems to be little barrier to further scaling.

A nanotube future?

There are, however, some pointed caveats to these findings. First, there’s the fact that IBM is only currently capable of building p-type transistors using this method. That doesn’t mean that the technology is useless — many of the proposed near-term solutions for improved silicon scaling rely on different materials for the p-channel and n-channel, but it definitely introduces additional complexity.
The International Technical Roadmap for Semiconductors hasn’t issued new reports since 2013; the group is currently evaluating changes to its measuring criteria and formulating new reports, but the 2013 data set is still online. Looking back at it, the roadmap for near-term introduction of carbon nanotubes wasn’t very rosy.

This chart shows the suitability of new materials compared to current methods, as well as the dates at which they might be introduced. Carbon nanotubes scored particularly badly in property control, contact viarability, and control of formation, location, and direction. IBM has claimed to have made substantial advances in all three areas since this report was written. In a 2014 discussion with The Register, IBM Researcher’s director of Physical Science, Supratik Guha stated: “You have to make carbon nanotubes with purity levels that are six nines. Today we are at four nines and over a year ago [we were] at 98.5 percent.” This aligns with the values listed in the 2013 ITRS reports, which were far too low to use for semiconductor manufacturing. IBM is pouring billions into researching CNTs, including each of these problems.
Keeping in mind that each additional “9” means a full order of magnitude improvement, CNTs still had a very long way to go in 2014. Solving the contact problem, however, would clear a substantial hurdle, possibly allowing for long-term adoption. If the goal is to bring the technology in at the 3nm node, there’s plenty of time to wait — while multiple sources that wrote up this story skipped this minor point, this prediction is a long time out. With nodes now shifting roughly every 30 months, we’re two years from 10nm and 5 years from 5nm. That puts the introduction of CNTs at the 3nm node, ~2023.